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STM32H563 (NUCLEO-H563ZI)

The STM32H563ZI (Cortex-M33 with TrustZone disabled, 2 MB flash, 640 KB SRAM) is LabWired's flagship hardware-validated Cortex-M33 target. A committed determinism report (examples/nucleo-h563zi/golden-reference/determinism_report_h563.json) records status: PASS over 50 compared steps of real silicon vs sim running the same ELF — see docs/golden_reference.md for the full pipeline.

Foreign-firmware digital twin (2026-06-11): an unmodified-logic embassy async example (USART3 + embassy-time on TIM12, thumbv8m) produces a byte-identical UART stream on the board's VCP and in the simulator — hello + 20 timer-paced ticks + DONE. The bring-up exercises PWR VOS, FLASH ACR, RCC, GPIO AF, USART3, TIM12 compare interrupts and the M33 acquire/release atomics end to end.

ST-HAL twin (same day): the unmodified STM32CubeH5 DMA_DataHandling example (full HAL stack — PWR Scale0, HSE+PLL1 @ 250 MHz, ICACHE, GPDMA channel 7 interrupt-driven with all seven data-handling modes: zero-pad / sign-extend / both truncations / SBX / DBX / DHX) reaches its success loop in the simulator and on the board — same ELF, same verdict, observed live over SWD (LED1 toggling, error LED dark).

For build/run instructions, see examples/nucleo-h563zi/README.md.

Status at a glance

Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard (level · modelled peripherals · register-match vs silicon) and the tier-1 matrix (per-peripheral pass/fail).

Aspect Status
Chip yaml configs/chips/stm32h563.yaml
System yaml configs/systems/nucleo-h563zi-demo.yaml
Reference firmware crates/firmware-h563-demo/, crates/firmware-h563-fullchip-demo/, crates/firmware-h563-io-demo/
Validation UART byte-parity vs silicon — determinism_report_h563.json records PASS; reset-state conformance (crates/core/tests/h563_conformance.rs) pinned to the 2026-06-10 silicon capture; GPIO MMIO diff (crates/hw-oracle/tests/h563_mmio_diff.rs) byte-exact vs silicon
Tier hardware-validated — full 13/13 tier1 class row (clock/gpio/uart/timer/dma/irq/i2c/spi/adc/pwm/wdt/rtc + can beachhead), every model silicon-diffed via h563_mmio_diff/h563_class_diff
HIL showcase examples/hil-displacement-showcase/
Silicon capture scripts/hw-capture-stm32h563.sh (AP1 dapdirect recipe — OpenOCD 0.12 has no stm32h5x.cfg and hla cannot reach AP1)

Peripherals (from chip yaml)

Peripheral Base Status Notes
Cortex-M33 — ✅ modeled Thumb-2 + FPU (TrustZone disabled)
SysTick 0xE000E010 ✅ hardware-parity Tick generation matches silicon byte-stream; CALIB silicon-pinned
RCC 0x44020C00 ✅ hardware-parity h5 profile — reset state + write behavior silicon-probed (gated SW→SWS, CAL-tracks-TRIM, RMVF, LSI/LSE ready rules)
GPIOA 0x42020000 ✅ hardware-parity stm32v2 MODER/AFR; reset values silicon-pinned (SWD pins)
GPIOB 0x42020400 ✅ hardware-parity Board LED LD1 (PB0); ODR/BSRR/BRR data path byte-exact vs silicon (h563_mmio_diff)
GPIOC 0x42020800 ✅ hardware-parity Reset values silicon-pinned
GPIOD 0x42020C00 ✅ hardware-parity USART3 alt-function pins
GPIOE 0x42021000 ✅ hardware-parity Full config surface parity-swept vs silicon
GPIOF 0x42021400 ✅ hardware-parity Board LED LD2 (PF4); config surface parity-swept
GPIOG 0x42021800 ✅ hardware-parity Board LED LD3 (PG4)
USART3 0x40004800 ✅ hardware-parity Virtual COM, IRQ 60 — byte-for-byte parity
USART1 0x40013800 ✅ silicon-pinned stm32v2 profile; ISR reset TXE|TC, BRR/CR1 round-trips bench-probed
USART2 0x40004400 ✅ silicon-pinned stm32v2 profile
LPUART1 0x44002400 ✅ silicon-pinned stm32v2 profile
TIM1 0x40012C00 ✅ silicon-pinned Advanced timer; PSC/ARR, UG→UIF, CNT run/freeze verified on silicon
TIM2 0x40000000 ✅ silicon-pinned 32-bit GP timer
TIM3 0x40000400 ✅ silicon-pinned GP timer
TIM6 0x40001000 ✅ silicon-pinned Basic timer (UG sets UIF only)
I2C1 0x40005400 ✅ silicon-pinned h5 profile (v2 IP layout); OAR1/TIMINGR/PE round-trips bench-probed
I2C2 0x40005800 ✅ silicon-pinned h5 profile
IWDG 0x40003000 ⚠ documented divergence Silicon commits PR/RLR only after LSI-domain sync; sim commits instantly (yaml-documented)
WWDG 0x40002C00 ✅ silicon-pinned CFR pinned; CR decrements live on silicon once clocked (not pinned)
CRC 0x40023000 ✅ hardware-parity Behavioral oracle: 0x12345678 → 0xDF8A8A2B matches silicon
RNG 0x420C0800 ⚠ documented divergence Sim assumes clocked, seeded RNG; silicon CR reset + kernel-clock errors documented in yaml
LPTIM1 0x44004400 ✅ modeled
GPDMA1 0x40020000 ✅ hardware-parity 8ch, software-request mem-to-mem silicon-verified (TCF/HTF, EN auto-clear, SAR/DAR advance); linked-list + peripheral-request modes not modeled
SPI1 0x40013000 ✅ hardware-parity stm32h5 v3 IP — CFG lock, mode-fault, CTSIZE/TXTF flags silicon-verified; data shift is sim-only (no spi_ker_ck on the bench, yaml-documented)
SPI2 0x40003800 ✅ silicon-pinned stm32h5 profile
SPI3 0x40003C00 ✅ silicon-pinned stm32h5 profile
ADC1 0x42028000 ✅ hardware-parity DEEPPWD/ADVREGEN/ADEN→ADRDY power-up silicon-verified; conversions sim-modeled; ADC2 not separately modeled
RTC 0x44007800 ✅ hardware-parity v3 calendar — WPR/init/BYPSHAD/INITS + calendar tick silicon-verified
TIM1 ch5/6 — ✅ hardware-parity CC5IF/CC6IF + compare-while-counting silicon-verified (PWM class)
NVIC 0xE000E100 ✅ hardware-parity ISER/ICER enable machinery diffed on the M33 (irq class)
PWR 0x44020800 ✅ hardware-parity H5 layout — VOSCR/VOSSR voltage scaling silicon-pinned (Scale3↔0↔2 transitions)
FLASH 0x40022000 ✅ silicon-pinned Interface regs (ACR latency read-back); program/erase not modeled
TIM12 0x40001800 ✅ silicon-pinned 2ch GP timer (foreign time-driver pick); resets + round-trips + free-run probed
DBGMCU 0x44024000 ✅ silicon-pinned IDCODE 0x10016484; CR plain R/W
FDCAN1 0x4000A400 ✅ hardware-parity M_CAN, fixed SRAMCAN layout — internal-loopback TX→RX FIFO0 silicon-verified (capture13, 22 diff cases); filtering/bit-timing/FDCAN2/IT1 not modeled (can class)

Not yet modeled (commonly expected on H563)

The chip yaml does not declare: I²C3/4, SPI4/5/6, ADC2, USART6, UART4/5/7/8/9/10/11/12, TIM4/5/7/8/12–17, DAC, OPAMP, USB-FS, OTFDEC, ETH, FDCAN1/2, OCTOSPI1/2, SDMMC1/2, GPDMA2, FLASH registers, ICACHE/DCACHE, TrustZone (SAU / IDAU), PKA / HASH / SAES.

Firmware that touches any of these will hit MemoryAccessViolation or stall in a polling loop. See docs/getting_started_firmware.md.

Validation runbook