STM32F405 (Feather-class)
The STM32F405RG (Cortex-M4F, 1 MB flash, 192 KB SRAM — 128 KB main declared,
64 KB CCM not modeled) is onboarded as a descriptor-level derivative of the
F401/F407 lane: it reuses the shared stm32f4 / stm32v2 peripheral
profiles, so every peripheral the F401 descriptor models behaves identically
here. It is smoke-validated, not hardware-validated — no F405 board has
been on the bench.
For build/run instructions, see
examples/feather-f405/README.md.
Status at a glance
Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard and the tier-1 matrix.
| Aspect | Status |
|---|---|
| Chip yaml | configs/chips/stm32f405.yaml |
| System yaml | configs/systems/feather-f405.yaml |
| Reference firmware | crates/firmware-f401-demo/ (link-compatible reuse — see VALIDATION.md) |
| Validation | UART2 smoke pass — see examples/feather-f405/VALIDATION.md |
| Tier | smoke-validated (UART2 only) |
| Hardware parity | Not byte-parity hardware-validated |
Peripherals (from chip yaml)
Same declared set as the F401 descriptor (RCC, GPIOA–C, USART1/2, I2C1,
SPI1, ADC1, TIM1/TIM2, DMA1/2, EXTI, RTC, IWDG, flash, PWR, DBGMCU with
F405 IDCODE 0x10006413, SysTick, NVIC). F405-only instances present on
silicon but not yet declared: I2C2, I2C3, SPI2, SPI3, USART3, USART6,
TIM3–5, RNG, CRYP/HASH — follow-up work, tracked against RM0090.