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STM32F401 (NUCLEO-F401RE)

The STM32F401RE (Cortex-M4F, 512 KB flash, 96 KB SRAM) is a Tier 1 LabWired target. The tier-1 fixture drives all twelve rubric classes (see the firmware-exercise matrix); the note below on I²C predates that and is kept for its history.

Timer input capture (2026-09-27): TIM1-5 and TIM9-11 declare input_capture: stm32f4. A pad muxed to TIMx_CHn (DS9716 AF1/AF2/AF3) feeds the channel: CCxS TI1/TI2/TRC, ICxF filter, ICxPSC, CCxP/CCxNP (rising/falling/both), CCRx latched at the edge cycle with CCxIF/CCxOF and the CCx interrupt, and PWM-input mode (slave reset on TI1FP1). Proven by register-level firmware in crates/core/tests/timer_input_capture.rs (HC-SR04 echo width; frequency/duty meter). Not modelled: the CCxDE DMA request (the STM32 DMA request map is not modelled for timers), the gated/trigger/external-clock slave modes, ITRx/ETR triggers, and the 2-3-cycle input resynchroniser delay of silicon.

I²C is being onboarded on F407 first — F407 hardware is on the bench, F401 isn't. Once the F407 lane is silicon-verified against the hardware oracle, the I²C1 yaml block ports to F401 as a zero-firmware-change delta. See docs/boards/stm32f407.md.

Package variant: the STM32F401CDU6 (384 KB flash, 96 KB SRAM) has its own chip descriptor (configs/chips/stm32f401cdu6.yaml) and a PR-run gate (firmware_survival::test_stm32f401cdu6_demo_survival, asserting OK over USART2). It shares this model.

For build/run instructions, see examples/nucleo-f401re/README.md.

Status at a glance

Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard (level · modelled peripherals · register-match vs silicon) and the tier-1 matrix (per-peripheral pass/fail).

Aspect Status
Chip yaml configs/chips/stm32f401.yaml
System yaml configs/systems/nucleo-f401re.yaml
Reference firmware crates/firmware-f401-demo/
Validation UART2 smoke pass — see examples/nucleo-f401re/VALIDATION.md
Tier smoke-validated (UART2 only)
Hardware parity Not byte-parity hardware-validated

Peripherals (from chip yaml)

Peripheral Base Status Notes
Cortex-M4F — ✅ modeled Thumb-2 + VFPv4 single-precision
SysTick 0xE000E010 ✅ modeled System-exception (15) path
RCC 0x40023800 ✅ modeled stm32f4 profile
GPIOA 0x40020000 ✅ modeled stm32v2 MODER/AFR layout
GPIOB 0x40020400 ✅ modeled Used for board LEDs
GPIOC 0x40020800 ✅ modeled Used for user button (PC13)
USART2 0x40004400 ✅ modeled Virtual COM port, IRQ 38 — byte-deterministic in smoke

Not yet modeled (commonly expected on F401)

The chip yaml currently does not declare any of the following, even though they are present on real F401RE silicon:

  • I²C1/2/3 — including the bus used by most external sensors. The external_devices attach pattern documented in examples/demo-blinky/ cannot be used on F401 until at least one I²C peripheral is added to configs/chips/stm32f401.yaml. Onboarding-in-flight on F407 — see docs/boards/stm32f407.md.
  • SPI1/2/3/4/5
  • DMA1/DMA2 — required for any HAL-style DMA-backed transfer
  • TIM1, TIM2–TIM5, TIM9–TIM11
  • ADC1
  • USB-OTG-FS, SDIO, I²S
  • PWR, FLASH controller registers
  • USART1, USART6

Firmware that touches any of these registers will hit MemoryAccessViolation or stall in a polling loop. See docs/getting_started_firmware.md for the diagnosis pattern.

Roadmap notes

F401 is a Tier 1 target (see docs/coverage_scoreboard.md). Closing the gap to a full Tier 1 model (DMA, timers, I²C, SPI) remains tracked work. The hardware-validation playbook to follow once peripherals are added is docs/boards/nucleo-l476rg.md — six survival tests asserting byte-for-byte UART parity with real silicon across UART, SPI, I²C, ADC, DMA, demo paths.