STM32F103 (Bluepill / demo-blinky)
The STM32F103C8 (Cortex-M3, 64 KB flash, 20 KB SRAM in the popular C8
package; this chip yaml advertises 1 MB / 128 KB to fit the full F103xE
memory map) is LabWired's reference Cortex-M3 target. It is the chip used
by examples/demo-blinky/, the
canonical example for attaching an external device model (TMP102) over
I²C.
For build/run instructions, see
examples/demo-blinky/README.md.
Status at a glance
Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard (level · modelled peripherals · register-match vs silicon) and the tier-1 matrix (per-peripheral pass/fail).
| Aspect | Status |
|---|---|
| Chip yaml | configs/chips/stm32f103.yaml |
| System yamls | configs/systems/stm32f103-bare.yaml, …-integrated-test.yaml, labwired-demo-board.yaml |
| Reference firmware | crates/firmware-stm32f103-blinky/, crates/firmware-stm32f103-uart/ |
| Tier | smoke-validated (UART + GPIO + I²C round-trip via demo-blinky) |
| Hardware parity | Not byte-parity hardware-validated (see L476 / H563 for the gold path) |
Peripherals (from chip yaml)
| Peripheral | Base | Status | Notes |
|---|---|---|---|
| Cortex-M3 | — | ✅ modeled | Thumb-2, no FPU |
| SysTick | 0xE000E010 | ✅ modeled | System-exception (15) path |
| RCC | 0x40021000 | ⚙ yaml-listed | F1 layout; no profile pinned in yaml |
| GPIOA | 0x40010800 | ✅ modeled | F1 CRL/CRH layout (not v2 MODER) |
| GPIOB | 0x40010C00 | ✅ modeled | F1 CRL/CRH layout |
| GPIOC | 0x40011000 | ✅ modeled | F1 CRL/CRH layout |
| USART1 | 0x40013800 | ⚙ yaml-listed | IRQ 37 |
| USART2 | 0x40004400 | ⚙ yaml-listed | IRQ 38 |
| I²C1 | 0x40005400 | ✅ modeled | Exercised via TMP102 round-trip in demo-blinky |
| I²C2 | 0x40005800 | ⚙ yaml-listed | IRQ 33 |
| AFIO | 0x40010000 | ⚙ yaml-listed | Alternate-function I/O remap |
| EXTI | 0x40010400 | ⚙ yaml-listed | External interrupt controller |
| DMA1 | 0x40020000 | ⚙ yaml-listed | No DMA stream survival test on this chip yet |
Not yet modeled (commonly expected on F103)
The chip yaml does not declare: SPI1/2, TIM1–TIM8, ADC1/2,
USB-FS, bxCAN, RTC, IWDG/WWDG, BKP, PWR. Firmware
that touches any of these registers will hit MemoryAccessViolation or
stall in a polling loop. See
docs/getting_started_firmware.md for
the diagnosis pattern.
Validation
- No
VALIDATION.mdfor an F103 board inexamples/yet; closest validation evidence is the I²C round-trip inexamples/demo-blinky/. - For the byte-parity validation pattern, see
docs/boards/nucleo-l476rg.md.