STM32F767 (NUCLEO-F767ZI)
The STM32F767ZI (Cortex-M7, 2 MB flash, 512 KB SRAM) is onboarded as a
descriptor-level derivative of the F4 lane: it reuses the shared stm32f4 /
stm32v2 peripheral profiles for RCC/GPIO/USART/SPI/timers/DMA/EXTI/RTC/
IWDG/flash/PWR, and the stm32l4 profile for I2C (the F7 I2C is the modern
v2 IP, not the F1/F4 legacy block). It is smoke-validated, not
hardware-validated — no F767 board has been on the bench.
For build/run instructions, see
examples/nucleo-f767zi/README.md.
Status at a glance
Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard and the tier-1 matrix.
| Aspect | Status |
|---|---|
| Chip yaml | configs/chips/stm32f767.yaml |
| Reference firmware | crates/firmware-f401-demo/ (link-compatible reuse — see VALIDATION.md) |
| Validation | UART smoke pass + clean instruction audit — examples/nucleo-f767zi/VALIDATION.md |
| Tier | smoke-validated (USART2 only) |
| Hardware parity | Not byte-parity hardware-validated |
Modeled (from chip yaml)
RCC (F4 profile), GPIO A–K, USART1/2/3/6, I2C1–4 (v2/stm32l4 profile),
SPI1–3, TIM1/TIM2, ADC1, DMA1/2, EXTI (24 lines), RTC, IWDG, flash, PWR,
DBGMCU (IDCODE 0x10006451), SysTick, NVIC.
Explicitly not modeled
F7-only RCC registers (PLLSAICFGR, DCKCFGR1/2 — peripheral clock muxing), Ethernet, LTDC/DMA2D, CAN, USB OTG FS/HS, SAI, QSPI, MDIOS, JPEG, DFSDM, FMC, SDMMC, ART accelerator reconfiguration. Sim86's own Nucleo-F767ZI page lists several of these as "present but nothing attached" — we declare nothing we do not model.