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nRF52840

Nordic nRF52840 — Cortex-M4F, 1 MB flash, 256 KB SRAM, 2.4 GHz radio, USB. LabWired models a full peripheral estate with silicon-verified register sweeps (Seeed XIAO nRF52840 Sense).

Live status

Status at a glance

Aspect Status
Chip descriptor configs/chips/nrf52840.yaml — 47 peripherals
Example system configs/systems/nrf52840-dk.yaml
Playground / form factor nRF52840-DK; XIAO nRF52840 Sense
Reference firmware crates/firmware-nrf52840-demo
Conformance crates/firmware-nrf52840-conformance
Tier silicon-verified (see below)

Flash / firmware artifact

Use Artifact Notes
Zephyr / bare-metal ELF Vector table at flash base per Nordic map
Arduino / PlatformIO Board compile profile output Hosted compile when board id registered
UF2 / SoftDevice — SoftDevice stacks: check whether your image expects radio stack blobs

Pins (nRF52840-DK / common)

Nordic pins are P0.xx / P1.xx. Playground and board-config map DK silkscreen to GPIO — always labwired_describe the board id you use.

Bank Role
P0.0–P0.31 GPIO0
P1.0–P1.15 GPIO1 (sim may remap base; see silicon notes below)
UART / SPI / TWI Via PSEL registers (not fixed Arduino pins only)

Support matrix (summary)

Block Status Notes
Cortex-M4F + FPU ✅ Thumb-2 + VFPv4
GPIO P0/P1 ✅ silicon-verified Strict register match
UART / SPIM / TIMER / RTC / WDT / RNG ✅ silicon-verified See harness table
RADIO / BLE air ✅ / ⚠️ RADIO registers + air model; not full BLE stack cert
USB ✅ / ⚠️ Modelled; edge cases may differ
CRYPTOCELL / NFC / QSPI / … ✅ modelled / verified subsets Scoreboard is authority

What it catches vs bench

Strong: GPIO/UART/SPI drivers, deterministic CI, register-level regressions vs silicon captures.
Bench: RF certification, analog SAADC accuracy, USB host edge cases, SoftDevice-only bugs.

How to run

CLI

cargo run -p labwired-cli -- run \
  --firmware path/to/zephyr.elf \
  --system configs/systems/nrf52840-dk.yaml

Playground

Open an nRF52840 / XIAO lab on app.labwired.com.

Agent

Connect MCP → labwired_describe → labwired_run / labwired_verify.

Three sim-vs-hardware harnesses, all run against live silicon over SWD:

Harness Scope Result
nrf52_mmio_diff production GPIO0/UART0/SPIM0 register paths 16/16 match
nrf52_onboarding_diff 22 peripherals, notable registers each 22/22 MODELLED
nrf52_gpio_conformance full GPIO register set, both ports P0 22/0, P1 23/0 (strict-clean)
nrf52_conformance behavioral digest (firmware on sim + silicon) 16/16 — re-confirmed on live silicon 2026-06-17 (all 3 former residuals closed)

Run them with --features hw-oracle-nrf52 -- --ignored. The reset-state capture truth-set lives in the private repo at validation/silicon/nrf52840/ (captured by scripts/hw-capture-nrf52840.sh).

Peripherals

Peripheral Base Status Notes
Cortex-M4F - modeled Thumb-2 + VFPv4 single-precision
GPIO P0 0x50000000 silicon-verified 32 pins; OUT/SET/CLR, DIR/SET/CLR, IN, PIN_CNF, DETECTMODE — strict-clean
GPIO P1 0x50000300¹ silicon-verified 16 pins (P1.0–P1.15); pins ≥16 correctly absent — strict-clean
UART0 0x40002000 silicon-verified nrf52 profile
SPIM0 0x40003000 silicon-verified ENABLE/PSEL/FREQUENCY/TXD/TASKS_START/EVENTS_END
TIMER0–4 0x40008000+ silicon-verified counter mode capture confirmed (CC[0])
RTC0–2 0x4000b000+ silicon-verified PRESCALER/CC
WDT 0x40010000 silicon-verified CRV reset 0xFFFFFFFF + config-lock-while-running²
RNG 0x4000d000 silicon-verified CONFIG; VALRDY liveness confirmed
RADIO 0x40001000 silicon-verified FREQUENCY/MODE/BASE
PWM0–3, SAADC, QSPI, PDM, I2S, PPI, GPIOTE, NFCT, COMP, QDEC, EGU0–5, ECB, TEMP, AAR, MWU, NVMC, UICR, FICR, USBD, ACL, CRYPTOCELL, CLOCK various modeled / silicon-verified declared in chip yaml; notable registers swept

¹ Silicon base. The sim remaps P1 to 0x50001000 to avoid GPIO0's 4 KB window; the conformance harness translates sim↔silicon addresses for P1. ² On the Seeed XIAO the UF2 bootloader starts the WDT before user code, so CRV reads its reset value and is write-locked — modeled faithfully.

Behavioral conformance (16/16) — former residuals now closed

The behavioral digest matches the 2026-06-09 silicon capture on every word. BASELINE_MATCHED in nrf52_conformance.rs is ratcheted at 16, and conformance_sim (no-hardware CI) asserts each field against the captured silicon value so the fixes can't regress:

  • ECB (AES-128): ecb.rs implements a real FIPS-197 AES-128 core driven over ECB EasyDMA → ciphertext word 0xD8E0C469 (matches silicon).
  • TEMP: temp.rs latches an in-range measurement on TASKS_START and fires EVENTS_DATARDY → temp_inrange = 1 (matches silicon).
  • GPIOTE task→GPIO: the GPIOTE SET task drives the pad/IN, not GPIO.OUT, so OUT stays 0 under these conditions (matches silicon). The plain GPIO register interface is separately strict-clean.

Re-confirmed on live silicon 2026-06-17 (Seeed XIAO nRF52840 Sense, ST-LINK V2 J37, SWD): conformance_diff reported 16/16 fields match (100%), and the full strict-mode sweep diverged on zero registers — nrf52_mmio_diff 16/16, nrf52_gpio_conformance P0 22/0 + P1 23/0, nrf52_onboarding_diff 22/22 MODELLED, plus POWER 10/0, SPIS 19/0, TWIS 20/0, RTC0 12/0, TIMER0 16/0, and SPIM0/CCM/full-register conformance all clean.