RP2350 (Raspberry Pi Pico 2)
The RP2350 (dual Cortex-M33, 2 MB XIP flash, 520 KB SRAM) is onboarded as a
descriptor-level derivative of the RP2040 lane: it reuses the RP2040
behavioural models for UART (PL011), I2C, SPI, DMA, PIO (v1-compatible on
PIO0–2), SIO, ADC, PWM, timer, and watchdog, with a profile: rp2350 on the
shared clock/reset model for the moved APB map. It is smoke-validated, not
hardware-validated — no Pico 2 has been on the bench.
For build/run instructions, see
examples/pico2/README.md.
Status at a glance
Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard and the tier-1 matrix.
| Aspect | Status |
|---|---|
| Chip yaml | configs/chips/rp2350.yaml |
| Reference firmware | crates/firmware-rp2350-demo/ (M33 bare-metal UART smoke) |
| Validation | UART smoke pass — examples/pico2/VALIDATION.md |
| Tier | smoke-validated (UART0 only) |
| Hardware parity | Not byte-parity hardware-validated |
Modeled (from chip yaml)
SYSINFO (CHIP_ID 0x30004927), CLOCKS/RESETS/XOSC/PLL_SYS/PLL_USB/ROSC
(rp2350 clkrst profile), UART0/1 (PL011), SPI0/1, I2C0/1, ADC, PWM,
TIMER0, WATCHDOG, DMA, PIO0/1/2 (v1 instruction set), SIO (core 0),
XIP_CTRL (declarative), POWERMAN/TICKS/TBMAN stubs, SysTick, NVIC.
Explicitly not modeled
TrustZone / security partitions, second M33 core and SIO FIFO dual-core bring-up, Hazard3 RISC-V cores, real bootrom + IMAGE_DEF boot path, USB device enumeration, HSTX/DVI, PIO v2-only instructions, OTP, SHA-256, TRNG, QMI programming. Sim86 claims several of these; we declare nothing we do not model.