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STM32H735VG

The STM32H735VG (Arm Cortex-M7 with FPU + MPU, up to 550 MHz, 1 MB flash, ~564 KB SRAM across DTCM/AXI/domain SRAMs) is the first fully-modelled Cortex-M7 chip in LabWired. It is an H7-family value-line part (RM0468 — STM32H723/733/725/735/730), distinct from the H5 in its memory map: GPIO at 0x5802_0000, RCC at 0x5802_4400, the flash interface at 0x5200_2000, and DBGMCU at 0x5C00_1000.

Onboarding it added a new H7 RCC register layout (rcc.rs Stm32H7): the enable block at AHB3ENR..APB4ENR (0xD4..0xF4), BDCR at 0x70 and CSR at 0x74, oscillator/PLL ready-bit gating (HSI→bit 2, CSI→8, HSE→17, PLL1→25, …) and the source-ready-gated SYSCLK switch (SW→SWS in CFGR). The remaining peripherals reuse the shared H7/H5 silicon IP already in the engine (gpio stm32v2, uart stm32v2, spi stm32h5, i2c h5, timer).

Fidelity: SIM-DERIVED. LabWired has no H735 bench part. Every reset value and behaviour is reference-manual-derived (RM0468 / DS13312), not a silicon capture. There is no reg_oracle and no MMIO diff for this chip yet. Promote to a higher tier only when a real H735 is diffed over SWD.

Status at a glance

Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard and the tier-1 matrix.

Aspect Status
Chip yaml configs/chips/stm32h735.yaml
System yaml examples/stm32h735-smoke/system.yaml
Fixture firmware examples/tier1-fixture/stm32h735/
Validation tier-1 fixture self-tests (clock/gpio/timer/pwm/i2c/spi/wdt/irq PASS + UART); io-smoke asserts the TIER1 transcript; chip_conformance estate OK
Tier sim-validated — reference-manual-derived, no silicon diff
Core type Arm Cortex-M7 (first M7 in the engine; bit-band correctly absent, like M33)

Modelled peripherals (from chip yaml)

  • RCC (Stm32H7 layout) — oscillator/PLL ready gating, SYSCLK switch gate, clock-enable round-trip.
  • GPIO ports A–H (stm32v2) — MODER/OSPEEDR/PUPDR/IDR/ODR/BSRR/BRR.
  • USART1/3 + LPUART1 (stm32v2) — ISR/RDR/TDR; USART3 is the console.
  • TIM1 (advanced, PWM) / TIM2 (32-bit) / TIM3.
  • I2C1/2 (h5, I2C v2 TIMINGR/ISR, AUTOEND NACK path).
  • SPI1/2 (stm32h5, SPI v2 CFG1/CFG2, EOT).
  • NVIC, IWDG, WWDG, CRC, RNG, DBGMCU.
  • PWR / FLASH interface — mapped as present (H5 layout) so HAL bring-up does not bus-fault; H7 VOSRDY / bank-2 semantics are not faithful.

Known omissions

H7 blocks whose IP diverges from the reused models — each reads as an unmapped hole until modelled: DMA (H7 DMA1/2 + BDMA + DMAMUX ≠ H5 GPDMA), ADC3 (16-bit / oversampling), RTC, FDCAN, OCTOSPI, Ethernet.

Runs real off-the-shelf firmware

Beyond the raw-register tier-1 fixture, two independent community HALs boot and run to completion on this model — the strongest fidelity signal short of silicon:

  • examples/stm32h735-hal-demo — unmodified stm32h7xx-hal: pwr.freeze() → rcc.freeze() (PLL1 to 200 MHz + FLASH latency + SYSCLK switch) → SYSCFG I/O-compensation cell → GPIO → HAL-configured USART3 printing 200000000 Hz sysclk.
  • examples/stm32h735-embassy-demo — embassy-stm32 async: embassy_stm32::init() (its own RCC/PWR/FLASH bring-up + peripheral-clock enables) → GPIO → async blink loop.

Both build hard-float (thumbv7em-none-eabihf) — the core now decodes Cortex-M7 double-precision VFP (VPUSH/VPOP/VLDM/VSTM .64, VLDR/VSTR.F64, VMOV.F64, VADD/VSUB/VMUL/VDIV.F64).

Run it

# raw-register peripheral self-tests
labwired run --chip configs/chips/stm32h735.yaml \
  --firmware tests/fixtures/tier1/stm32h735.elf --max-steps 5000000
# → TIER1 clock PASS … TIER1 irq PASS … TIER1 done

# real stm32h7xx-hal firmware (build soft- or hard-float)
cargo build --release --target thumbv7em-none-eabihf \
  --manifest-path examples/stm32h735-hal-demo/Cargo.toml
labwired run --chip configs/chips/stm32h735.yaml \
  --firmware examples/stm32h735-hal-demo/target/thumbv7em-none-eabihf/release/stm32h735-hal-demo \
  --max-steps 20000000
# → HAL: DONE / tick 1 …