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RP2040

Raspberry Pi RP2040 (dual Cortex-M0+, 264 KB SRAM, external QSPI flash, PIO). LabWired Tier-1 target — useful for bring-up, with honest gaps below.

Live status

Status at a glance

Aspect Status
Chip descriptor configs/chips/rp2040.yaml
Systems configs/systems/pico.yaml, configs/systems/rp2040-pico.yaml
Playground Raspberry Pi Pico / related board ids in board-config
Reference firmware crates/firmware-rp2040-pio-onboarding/
Tier Structural / growing — read matrix before CI claims

Flash / firmware artifact

Use Artifact Notes
Pico SDK / bare-metal ELF or UF2-derived image as supported by loader Match memory map in chip yaml
Arduino-Pico Compile profile output Hosted compile when registered

Pins (Raspberry Pi Pico)

Silk GPIO Notes
GP0–GP28 GPIO0–28 Standard Pico header map
3V3 / GND Power Digital twin
ADC GPIOs GP26–29 ADC modelling may be partial

Always confirm with labwired_describe for the exact board id.

Support matrix

Block Status Notes
Cortex-M0+ core 0 ✅ Instruction path
Core 1 (second M0+) ❌ / ⚠️ Not a complete dual-core product story yet
UART0 ✅ Modelled (check register profile notes in chip yaml)
PIO0 ⚠️ Yaml-listed; full SM execution depth limited
GPIO / SIO / DMA / USB / ADC / SPI / I²C / PWM ⚠️ / ❌ Many blocks incomplete — unmodeled access → fault or stall
External QSPI XIP ⚠️ Flash load path depends on image

Firmware that touches unmodeled MMIO will hit MemoryAccessViolation or poll forever — that is intentional honesty.

What it catches vs bench

Strong: Single-core logic demos that stay on modelled peripherals; agent/CLI oracle loops when assertions match reality.
Bench / later: Full PIO programs, dual-core + SIO FIFOs, USB device stack, timing-sensitive bit-banging on incomplete GPIO.

How to run

CLI

cargo run -p labwired-cli -- run \
  --firmware path/to/firmware.elf \
  --system configs/systems/pico.yaml

Playground

Pico-class lab on app.labwired.com.

Agent

MCP → describe board → run → verify. Do not claim PIO/USB success if the matrix says otherwise.