nRF52832

The Nordic nRF52832 (Cortex-M4F, 512 KB flash, 64 KB SRAM, 2.4 GHz radio) is a Tier 1 LabWired target. The current model is uart-only — UART0 is the only on-chip peripheral declared. Everything else (radio, EasyDMA, PPI, GPIO, RTC, TIMER, TWI/SPI) is not yet declared in the chip yaml.

Status at a glance

Live status: the table below is a hand-maintained snapshot. For the authoritative, auto-generated view see the chip conformance scoreboard (level · modelled peripherals · register-match vs silicon) and the tier-1 matrix (per-peripheral pass/fail).

Aspect	Status
Chip yaml	configs/chips/nrf52832.yaml
System yaml	configs/systems/nrf52-dk.yaml
Reference firmware	None — no per-board demo crate exists yet
Tier-1 fixture	examples/tier1-fixture/nrf52832
Validation	No VALIDATION.md checked in
Tier	structural — UART0 model only, no in-tree validation runbook

Peripherals (from chip yaml)

Peripheral	Base	Status	Notes
Cortex-M4F	—	✅ modeled	Thumb-2 + VFPv4 single-precision
UART0	0x40002000	✅ modeled	nrf52 profile — uses Nordic register layout, not ARM PrimeCell

Not yet modeled (commonly expected on nRF52832)

The chip yaml does not declare: CLOCK, POWER, RADIO, TIMER0–4, RTC0–2, GPIO P0 (0x50000000), GPIOTE, TWI0/1 (I²C), SPI0/1/2, TWIM/TWIS, PPI (programmable peripheral interconnect), EasyDMA infrastructure, RNG, TEMP, WDT, NVMC, UICR, FICR, SAADC, ECB, CCM, AAR.

Firmware that touches any of these registers will hit MemoryAccessViolation or stall in a polling loop. See docs/getting_started_firmware.md.

Roadmap notes

nRF52832 is a Tier 1 target (see docs/coverage_scoreboard.md). Closing the gap to a full Tier 1 model requires at minimum: CLOCK, POWER, RADIO, GPIO P0, TIMER0, RTC0, and PPI. The hardware-validation playbook to follow once peripherals are added is docs/boards/nucleo-l476rg.md.