Skip to content

Validation Report: renesas-rz_t2m_rsk

Architecture: Dual ARM Cortex-R52.

1. Dynamic Simulation Validation

Status: ✅ Passed (simulation-ok)

2026-10-18T14:40:21.157763Z  INFO labwired_cli::commands::run: Starting LabWired Simulator
2026-10-18T14:40:21.161674Z  INFO labwired_core::system::builder: Loading chip descriptor: ../../chips/onboarding/renesas-rz_t2m_rsk.yaml
2026-10-18T14:40:21.308749Z  INFO labwired_cli::commands::run: Loading firmware: "/home/andrii/Projects/labwired-renode/core/tests/fixtures/uart-ok-thumbv7m.elf"
2026-10-18T14:40:21.308858Z  INFO labwired_loader: ELF Entry Point: 0x401
2026-10-18T14:40:21.308869Z  INFO labwired_cli::commands::run: Firmware Loaded Successfully!
2026-10-18T14:40:21.308874Z  INFO labwired_cli::commands::run: Entry Point: 0x401
2026-10-18T14:40:21.313228Z  INFO labwired_cli::commands::run: Starting Simulation (ARM Cortex-M)...
2026-10-18T14:40:21.313302Z  INFO labwired_cli::commands::run: Initial PC: 0x400, SP: 0x20020000
2026-10-18T14:40:21.313339Z  INFO labwired_cli: Running for 20000 steps...
2026-10-18T14:40:21.313467Z  INFO labwired_cli: Simulation Error at step 2: Memory access violation at 0x2001ffe0
2026-10-18T14:40:21.313519Z  INFO labwired_cli::report: Simulation loop finished.
2026-10-18T14:40:21.313545Z  INFO labwired_cli::report: Final PC: 0x45c
2026-10-18T14:40:21.313569Z  INFO labwired_cli::report: Total Instructions: 2
2026-10-18T14:40:21.313592Z  INFO labwired_cli::report: Total Cycles: 2
2026-10-18T14:40:21.313613Z  INFO labwired_cli::report: Average IPS: 422.41

Hardware Coverage Report

Peripheral ID Base Address Type
timer 0x0000000f arm_generictimer
sci0 0x80001000 renesas_sci
sci1 0x80001400 renesas_sci
sci2 0x80001800 renesas_sci
sci3 0x80001c00 renesas_sci
sci4 0x80002000 renesas_sci
sci5 0x81001000 renesas_sci

Total Peripherals: 7