S32K388EVB-Q289
The NXP S32K388EVB-Q289 evaluation board with an S32K388 in a 289
MAPBGA. Only the boot core, CM7_0 (Cortex-M7), is modelled: 8 MiB of program
flash at 0x0040_0000 (the boot header at the base, the vector table at
0x0040_1000), SRAM_0–2 (768 KiB) at 0x2040_0000, the green user LED on
PTF23 and the console on LPUART2.
This is the LPUART+LED L1 slice and the first S32K3 part. Boot, the
LPUART2 console and the SIUL2 GPIO path on the six RGB LED pads (through the
GPDO bytes, PGPDO and MPGPDO, with GPDI/PGPDI read-back) are proven
by a committed smoke fixture and an io-smoke.yaml. SIUL2 is a new model
(s32k3_siul2); LPUART0–15 reuse the i.MX RT LPUART model, which has the
same register layout.
Not claimed yet
The boot ROM and HSE are not modelled and the boot header is not parsed:
the engine boots from 0x0040_1000 (reset_vector_offset). MC_ME,
MC_CGM, the oscillators/PLL, PMC and SWT_0 are declared stubs, so clock
gating has no effect, the core stays at the 48 MHz FIRC reset clock and
the watchdog never fires. The SIUL2 input mux (IMCR), INV and the
external interrupts are not modelled. SRAM ECC, the caches, TCM use, MPU
and FPU are not exercised. CM7_1–3 and the lockstep checkers are not
modelled. FlexCAN, LPSPI, LPI2C, eMIOS, eDMA, GMAC, ADC, PIT, RTC,
QuadSPI and the rest are not mapped: firmware that touches them
faults with a memory violation. There is no silicon capture:
SIM-DERIVED.
Live status
The tables below are a maintained snapshot. Authoritative automation:
- Chip conformance scoreboard — level · modelled peripherals · register-match
Status at a glance
| Aspect | Status |
|---|---|
| Chip descriptor | configs/chips/s32k388.yaml |
| Example system | configs/systems/s32k388-evb.yaml |
| Reference firmware | crates/firmware-s32k388-evb-smoke/ |
| Example | examples/s32k388-evb/ |
| Committed artifact | tests/fixtures/s32k388-evb-smoke.elf (S32K388 EVB SMOKE) |
| Build target | thumbv7em-none-eabi |
| Tier (snapshot) | L1 — smoke (CM7_0 + memory + SIUL2 + LPUART2); SIM-DERIVED |
Memory map and board wiring
| Region / signal | Base / pin | State |
|---|---|---|
| ITCM (CM7_0 view) | 0x0000_0000, 32 KiB |
mapped as plain RAM, not exercised |
| Program flash | 0x0040_0000, 8 MiB |
modelled — boot header at the base, vector table at 0x0040_1000; the last 176 KiB (HSE firmware on silicon) are plain flash here |
| DTCM (CM7_0 view) | 0x2000_0000, 64 KiB |
mapped as plain RAM, not exercised |
| SRAM_0–2 | 0x2040_0000, 768 KiB |
modelled — stack at the top; ECC not modelled |
| MSCM, PFLASH, SWT_0, STM_0, XRDC, DMAMUX0/1, MC_RGM | 0x4026_0000 … 0x4028_C000 |
type: stub |
| SIUL2 | 0x4029_0000 |
modelled (s32k3_siul2) |
| SIRC/SXOSC/FIRC/FXOSC, MC_CGM, MC_ME, PLL/PLL_AUX, PMC, flash controller | 0x402C_8000 … 0x402E_C000 |
type: stub |
| LPUART0–7 | 0x4032_8000 + 0x4000×n, IRQ 141–148 |
modelled (imxrt_lpuart); LPUART2 is the console |
| LPUART8–15 | 0x4048_C000 + 0x4000×n, IRQ 149–156 |
modelled (imxrt_lpuart), not exercised |
| Green LED (D78) | PTF23 (MSCR 183) |
modelled GPIO — active high |
| Other RGB LED pads (D77 R/G/B, D78 R/B) | PTF17/18/19, PTF22/24 |
modelled GPIO; from the Renode board file only |
| SW10 | PTA1 (MSCR 1) |
modelled GPIO input; read with the internal pulls only |
| LPUART2 console | — | the simulator captures the LPUART2 stream; the USB-UART bridge and its pads are not confirmed or modelled |
Boot path
Fast boot. On silicon the boot ROM reads the boot header (IVT, marker
0x5AA55AA5) at 0x0040_0000 and starts CM7_0 at the address in its CM7_0
slot (IVT + 0x0C). The engine does not run the boot ROM or parse the IVT:
its first two words are not a valid SP/PC pair, so the chip's
reset_vector_offset: 0x1000 makes reset load SP/PC from 0x0040_1000, the
address the RTD template and the smoke put in that slot (reset handler
0x0040_1400, SP 0x204C_0000).
Validation
# from the repository root
cargo build -p firmware-s32k388-evb-smoke --release --target thumbv7em-none-eabi
./target/release/labwired test --script examples/s32k388-evb/io-smoke.yaml --no-uart-stdout
See examples/s32k388-evb/VALIDATION.md
for the claims, runtime evidence and explicit non-claims.
Sources
The NXP RTD S32K388 device headers and SVD (peripheral bases, interrupt
numbers, register layouts, reset values), the S32DS RTD linker and
ivt_config.c templates (memory map, boot header), the Zephyr SIUL2 GPIO
driver (parallel-port bit order) and the Renode v1.17.0 S32K388 platform as a
cross-check — detailed in
examples/s32k388-evb/REQUIRED_DOCS.md.